In general, latch circuits are used for holding and storing input signals. Latch circuits are formed of, for example, metal oxide semiconductor (MOS) transistors that switch between an electrically connecting state (hereinafter, “ON-state”) and an electrically disconnecting state (hereinafter, “OFF-state”) according to inverters that invert input signals or gate voltage. In recent years, as disclosed in, for example, Japanese Laid-open Patent Publication No. 2006-41760, latching of an optical signal obtained by a photodiode has been proposed, which uses a latch circuit having a small mounting area.
FIG. 6 is a circuit diagram of a configuration of the latch circuit disclosed in the above Publication. In this latch circuit, the optical signal input to a photodiode 40 is latched by a loop including an inverter 50 and an inverter 60.
More particularly, while a gate formed of a P-channel MOS transistor 20 and an N-channel MOS transistor 30 is in the OFF-state according to a gate signal MCK and an inverted gate signal XMCK, a refresh signal R changes to “0” level to switch a P-channel MOS transistor 10 into the ON-state. Accordingly, a positive power supply voltage is continuously applied to an input terminal IN and the photodiode 40 to accumulate electric charge in a capacitor of the photodiode 40, until the refresh signal R changes to “1” level to switch the P-channel MOS transistor 10 into the OFF-state.
If an optical signal is input to the photodiode 40 after the refresh signal R changes to “1” level, the photodiode 40 switches into the ON-state, the electric charge accumulated in the capacitor is discharged, and the voltage of the input terminal IN changes to “0” level. As this happens, an output Q obtained as a result of inverting an input voltage by the inverter 50 is at “1” level, and an inverted output QX obtained as a result of inverting the output Q by the inverter 60 is at “0” level.
Subsequently, when the gate signal MCK and the inverted gate signal XMCK are inverted and the gate formed of the P-channel MOS transistor 20 and the N-channel MOS transistor 30 switches into the ON-state, the loop including the inverter 50 and the inverter 60 functions as the latch circuit to latch the optical signal input to the photodiode 40 stably.
However, in the conventional latch circuits, output timings of an output and an inverted output differ from each other. For example, in the latch circuit disclosed in the above Publication, because the inverted output QX is obtained by inverting the output Q by the inverter 60, an output timing of the inverted output QX is delayed by a time taken by the inverter 60 to perform the inversion.
More particularly, as illustrated in FIG. 7, when latching an input signal DIN, the input signal DIN is input when the gate signal MCK is at “0” level (i.e., when the inverted gate signal XMCK is at “1” level), and while the gate signal MCK is at “1” level (i.e., while the inverted gate signal XMCK is at “0” level), the latched input signal DIN is output as the output Q and as the inverted output QX. The output timing of this output Q is delayed from the output timing of the input signal DIN at least by a time taken by the inverter 50 to perform the inversion. Further, the output timing of this inverted output QX is delayed from the output timing of the output Q by a time taken by the inverter 60 to perform the inversion. As a result, the output timings of the output Q and the inverted output QX do not coincide with each other.
If such a latch circuit is used for, for example, a random access memory (RAM), a time difference may be generated between an output of a write signal and an output of a read signal, which have an inversion relation to each other. As a result, writing and reading may be performed at the same time, or both writing and reading may not be performed, resulting in the RAM not operating normally.